1. Field of the Invention
The present invention relates generally to devices and circuits providing electrostatic discharge (ESD) protection, and more particularly, to devices and circuits providing ESD protection to high voltage laterally diffused metal oxide semiconductor (LDMOS) transistors.
2. Description of the Related Art
The following descriptions and examples are given as background information only.
As is well known in the microelectronics industry, integrated circuit devices are susceptible to damage from application of excessive voltages, such as, for example, electrostatic discharge (ESD) events. In particular, during an ESD event, charge transferred within a circuit can develop voltages that are large enough to break down insulating films (e.g., gate oxides) on the device or dissipate sufficient energy to cause electro-thermal failures in the device. Such failures include contact spiking, silicon melting, or metal interconnect melting. As such, protection circuits are often connected to I/O bonding pads of an integrated circuit to safely dissipate energy associated with ESD events away from active circuitry. Protection circuits may also be connected to power supply pads or between power supply buses to prevent damage to active circuitry. In developing effective ESD protection circuitry, circuit designers may, however, be limited with regard to the particular structures used, since the protection circuit must integrate well with the remainder of the integrated circuit. For instance, integrated circuits which operate with applications of high voltages (i.e., VDD>12 volts) generally need protection circuitry configured to accommodate high voltage levels.
A transistor structure often used for high voltage applications is a drain extended metal oxide semiconductor (DEMOS) transistor, which may also be referred to in the microelectronics industry as a laterally diffused metal oxide semiconductor (LDMOS) transistor. DEMOS transistors differ from other MOS transistors in that the drain contact region is laterally displaced apart from the channel of the transistor at a greater distance than the source contact region of the transistor. As a consequence of the additional voltage drop in the drain extension region, the voltage across the channel of the DEMOS transistor is lower than a transistor having a drain contact region closer to the transistor gate and, in turn, the electric field across the gate oxide is lower. Although DEMOS transistors are effective for operations at high voltage levels, DEMOS transistors are inherently susceptible to damage from ESD events due to their device structure.
One approach in providing ESD protection for integrated circuits having DEMOS transistors is to employ a silicon controlled rectifier (SCR) type structure for transferring charge away from the transistor. For example, some conventional designs incorporate SCRs within active DEMOS transistors of an integrated circuit (i.e., transistors used for operations of a device other than protection from ESD events). Such a configuration, however, relies on drain breakdown of the active DEMOS transistor to trigger the SCR. In some cases, triggering the SCR in such a manner may not be fast enough to prevent the active DEMOS transistor from being damaged and, therefore, may not be effective for many applications. In other embodiments, an SCR may be incorporated within protection circuitry coupled to I/O bonding pads of an integrated circuit. In some cases, a protection-designated DEMOS transistor may further be included in the protection circuitry to trigger the SCR. In general, however, such configurations have limited controllability of the trigger and holding voltages of the SCR, specifically relative the breakdown voltage of the DEMOS transistor within the protection circuitry. More specifically, conventional designs do not offer layouts in which trigger and holding voltages of the SCR as well as the breakdown of the protection circuitry DEMOS transistor can be independently set. As a consequence, the level of ESD protection offered by such prior art designs is limited.
Accordingly, it would be beneficial to develop an improved ESD protection circuit suitable for use with an integrated circuit utilizing high voltage drain extended MOS transistors. In particular, it would be advantageous to develop an ESD protection device that allows the trigger and holding voltages of an incorporated SCR as well as the breakdown of an incorporated DEMOS transistor to be independently set. In addition, it would be valuable to arrange such protection circuitry in a variety of manners within an integrated circuit such that energy associated with ESD events may be safely dissipated from different types of circuit devices, including but not limited to pull down output transistors and/or pull up output transistors.